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| HD151TS305RP Spread Spectrum Clock for EMI Solution REJ03D0021-0900Z Rev.9.00 Jul. 07, 2004 Description The HD151TS305 is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution. Features * * * * Supports 60 MHz to 160 MHz operation. (Designed @ SSCCLKOUT = 72 MHz) 1 copy of finx4 clock out with Spread Spectrum Modulation @3.3 V 1 copy of reference clock @3.3 V Programmable Spread Spectrum Modulation (0.25%, 0.5%, 1.5% Central Spread Modulation and Spread Spectrum disable mode) * SOP-8pin Key Specifications * * * * * Supply Voltages: VDD = 3.3 V 0.165 V 0 to 70C (Ta) Operating Range 50 5% Outputs Clock Duty Cycle Cycle to Cycle jitter = 250ps typ. Ordering Information Part Name HD151TS305RPEL Package Type SOP-8 pin (JEDEC) Package Code FP-8DC RP Package Abbreviation Taping Abbreviation (Quantity) EL (2,500 pcs / Reel) Note: Please consult the sales office for the above package availability. Block Diagram VDD GND CLKOUT (12MHz typ.) XIN OSC XOUT R=1 M 1/n SSC Modulator 1/m Synthesizer SSCCLKOUT (48MHz typ.) R=100 k SEL0 R=100 k SEL1 Mode Control Rev.9.00 Jul. 07, 2004 page 1 of 9 HD151TS305RP Pin Arrangement SSCCLKOUT 1 8 SEL1 VDD 2 7 CLKOUT GND 3 6 SEL0 XIN 4 5 XOUT (Top view) SSC Function Table SEL1 :0 00 01 10 11 0.5% 1.5% SSC OFF 0.25% Spread Percentage Note: 0.25% SSC is selected for default by internal pull-up resistors. Clock Frequency Table XIN(MHz) 15 40 60 *1 *1 SSCCLKOUT(MHz) 15 *2 CLKOUT(MHz) 40*2 160 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. Pin Descriptions Pin name GND VDD CLKOUT SSCCLKOUT XIN XOUT SEL0 SEL1 3 2 7 1 4 5 6 8 No. Type Ground Power Output Output Input Output Input Input GND pin Power supplies pin. Normally 3.3 V. Normally 3.3 V reference clock output. Spread spectrum modulated clock output. Oscillator input. Oscillator output. SSC mode select pin. LVCMOS level input. Pull-up by internal resistor (100 k). SSC mode select pin. LVCMOS level input. Pull-up by internal resistor (100 k). Description Rev.9.00 Jul. 07, 2004 page 2 of 9 HD151TS305RP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Tstg Symbol VDD VI VO IIK IOK IO -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD+0.5 -50 -50 50 0.7 -65 to +150 Ratings V V V mA mA mA W C VI < 0 VO < 0 VO = 0 to VDD Unit Conditions Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Supply voltage DC input signal voltage High level input voltage Low level input voltage Operating temperature Input clock duty cycle VIH VIL Ta Symbol VDD Min 3.135 -0.3 2.0 -0.3 0 45 -- -- -- -- 50 Typ 3.3 Max 3.465 Unit V Conditions VDD+0.3 V VDD+0.3 V 0.8 70 55 V C % DC Electrical Characteristics Ta = 0 to 70C, VDD = 3.3 V5% Item Input low voltage Input high voltage Input current Symbol VIL VIH II -- 2.0 -- -- Input slew rate Input capacitance Operating current Note: CI 1 -- -- Min -- -- -- -- -- -- 20 Typ *1 Max 0.8 -- 10 100 4 4 -- V V Unit Test Conditions A VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins V / ns pF mA 20% - 80% SEL0, SEL1 XIN = 18 MHz, CL = 0 pF, VDD = 3.3 V 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Rev.9.00 Jul. 07, 2004 page 3 of 9 HD151TS305RP DC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 0 to 70C, VDD = 3.3 V5% Item Output voltage Output current *1 Note: Symbol VOH VOL IOH IOL 3.1 -- -- -- Min -- -- -40 40 Typ -- 50 -- -- Max V mV mA Unit Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.5 V VOL = 1.5 V 1. Parameters are target of design. Not 100% tested in production. AC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 25C, VDD = 3.3 V, CL = 15 pF Item Cycle to cycle jitter *1, 2 Symbol tCCS -- Min Typ | 250 | Max | 300 | Unit ps Test Conditions SSCCLKOUT = 72MHz, XIN = 18 MHz SSCCLKOUT = 72MHz, XIN = 18 MHz CLKOUT=18MHz Notes SSC = 0% SEL1:0 = 10 Fig1 SSC = 0.25% SEL1:0 = 11 Fig1 Fig1 SSC = 0% SEL1:0 = 10 SSC= 0.25% SEL1:0 = 11 0.4 V to 2.4 V -- | 250 | | 300 | -- Output frequency *1, 2 | 250 | -- -- -- 50 40 33 -- -- | 300 | 73.6 73.7 -- 55 -- -- 40 2 V/ns % KHz MHz ms MHz 70.4 70.3 SSCCLKOUT = 72MHz, XIN = 18 MHz SSCCLKOUT = 72MHz, XIN = 18 MHz XIN = 18 MHz CLKOUT Slew rate*1 Clock duty cycle *1 *1 tSL 0.8 45 -- -- 15 -- Output impedance Spread spectrum modulation frequency *1 Input clock frequency Stabilization time Note: *1,3 SSCCLKOUT = 96MHz, XIN = 24 MHz 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. SSCCLKOUT (or CLKOUT) tcycle n tcycle n+1 t CCS = (tcycle n) - (tcycle n+1) Figure 1 Cycle to cycle jitter Rev.9.00 Jul. 07, 2004 page 4 of 9 HD151TS305RP Application Information 1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed, as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type. R1 SSCCLKOUT 1 8 SEL1 R2 VDD C2 C1 3 6 SEL0 2 7 CLKOUT TS300 Series GND GND 4 GND XIN (Crystal or Reference input) XOUT (Crystal or Not connection) 5 Notes: C1 = High frequency supply decoupling capacitor. (0.1 F recommended) C2 = Low frequency supply decoupling capacitor. (22 F tantalum type recommended) R1, R2 = Match value to line impedance. (22 Reference value) Figure 2 Recommended circuit configuration Rev.9.00 Jul. 07, 2004 page 5 of 9 HD151TS305RP 2. Example Board Layout Configuration VDD (+3.3 V Supply) P FB 22 F G R1 SSCCLKOUT 0.1 F G 1 8 R2 7 CLKOUT G 3 6 4 5 Crystal connection or Reference input Note: Crystal connection or Not connection G Via to GND plane R1, R2 = Match value to line impedance. (22 Reference value) FB = Ferrite bead. Figure 3 Example Board Layout Rev.9.00 Jul. 07, 2004 page 6 of 9 HD151TS305RP 3. Example of TS300 EMI Solution IC's Application Spread Spectrum Modulated Clock XIN XOUT TS30X SSC CLKOUT Ref. Clock 3.3 V CMOS level ref. Clock CPU & ASIC XTAL Memory Graphics System Cont. Fig 4 Ref. Clock Input Example Spread Spectrum Modulated Clock XIN XTAL XOUT TS30X SSC CLKOUT CPU & ASIC Memory Graphics System Cont. System BUS System BUS Fig 5 XTAL Ref. Clock Input Example Rev.9.00 Jul. 07, 2004 page 7 of 9 HD151TS305RP 4. Recommendation of Power-ON Sequence We recommend usage as power-on sequence Vdd starting profile. At the time of power-on starting, there is possibility for SSCCKOUT to fix Hi/Low level. Please refer Fig6-1 and Fig6-2. VDD Power ON Upper 2.8V delay XIN XIN XOUT Ref. Clock Input Timing of XIN (XIN should be applied after Vdd 2.8V) Fig 6-1 In case of reference clock input VDD Power ON 2.8V Over 3.5V/msec XIN XIN XOUT X' tal Minimal Rising Time (Vdd rising time should be applied over 3.5V/msec) Fig 6-2 In case of X'tal reference input 5. Cycle to Cycle Jitter We have guaranteed that cycle to cycle jitter will be less than |300ps| at XIN=18MHz, Vdd=3.3V. In case of using XIN will be less than 15MHz, the cycle to cycle jitter may be over |300ps|. Please notice to consider this point. Rev.9.00 Jul. 07, 2004 page 8 of 9 HD151TS305RP Package Dimensions As of January, 2003 Unit: mm 4.90 5.3 Max 5 8 1 4 3.95 *0.22 0.03 0.20 0.03 1.75 Max 0.75 Max 6.10 - 0.30 + 0.10 1.08 0 - 8 0.14 - 0.04 + 0.11 1.27 + 0.67 0.60 - 0.20 *0.42 0.08 0.40 0.06 0.15 0.25 M *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-8DC Conforms -- 0.085 g Rev.9.00 Jul. 07, 2004 page 9 of 9 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. 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The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. 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